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Ordering number : EN*5966
CMOS IC
LC74793, 74793JM
VPS / PDC Slicer IC
Preliminary Overview
The LC74793/JM is a CMOS IC that provides PDS, VPS, and UDT data acquisition functions. The LC74793/JM supports microprocessor control of its operating modes and microprocessor read out of data acquired in any of its operating modes.
Package Dimensions
unit: mm 3067-DIP24S
[LC74793]
Features
* VPS data acquisition (5 or 11 to 15 bytes) VPS: Video Program System * PDC (8/30/2) data acquisition (13 to 25 bytes) PDC: Program Delivery Control * UDT (8/30/1) data acquisition (13 to 25 bytes) UDT: Unified Date and Time * Header (X/00) data acquisition (14 to 45 bytes) * Status display (8/30/1, 8/30/2) data acquisition (26 to 45 bytes) * Automatic VPS/PDC discrimination mode * Built-in AFC and sync separator circuits * Synchronization discrimination circuit * I2C bus support
SANYO: DIP24S
unit: mm 3112-MFP24S
[LC74793JM]
SANYO: MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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D1898RM (OT) No. 5966-1/24
LC74793, 74793JM Pin Assignment
No. 5966-2/24
LC74793, 74793JM Pin Functions
Pin No. 1 2 3 4 5 6 Pin VSS1 Xtalin Xtalout CTRL1 NC SDA Data I/O I2C bus Clock input I2C bus External synchronizing signal discrimination output Horizontal synchronizing signal output Ground Charge pump output Oscillator control voltage input Oscillator range adjustment Data acquisition output Power supply (+5 V) Sync separator circuit input Slice level output Composite synchronizing signal output Vertical synchronizing signal input PDC/VPS data I/O. I2C bus write address: 01111100 I2C bus read address: 01111101 PDC/VPS data clock input. I2C bus External synchronizing signal presence/absence discrimination status output. A high level is output when synchronizing signals are present. This pin outputs the crystal oscillator clock when the RST pin is low. (This reset state output can be disabled with command input.) Horizontal synchronizing signal output Ground. (VCO circuit ground) Charge pump output. Connect a low-pass filter to this pin. VCO oscillation control voltage input VCO oscillation range adjustment resistor connection Outputs a low level when PDC/VPS data has been discriminated Power supply (+5 V) (VCO system power supply) Internal sync separator circuit video signal input Slice level verification Internal sync separator circuit composite synchronizing signal output Inputs the vertical synchronizing signal by integrating the SEP out pin output signal. Applications must connect the SEP out pin to this pin through an integration circuit. If unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.) Vertical synchronizing signal output This pin outputs the VCO clock when the RST pin is low. (This reset state output can be disabled with command input.) Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPin input. When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.) When high: The VSYNC signal is input. Connection for the clock phase adjustment resistor. System reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Power supply. (+5 V: digital system power supply) Ground Crystal oscillator connections Crystal element switching Function Digital system ground Connections for the crystal element and capacitors that form the crystal oscillator. Also used for external clock input (fsc, 2fsc, or 4fsc). Switches between external clock input mode and crystal oscillator mode. Set this pin low for crystal oscillator, and high for external clock input. Description
7
SCL
8
SYNCJDG Hout VSS2 CPOUT VCOIN VCOR DAV VDD2 SYNin SEPC SEPOUT SEPIN
9 10 11 12 13 14 15 16 17 18 19
20
Vout
Vertical synchronizing signal output
21
CTRL2
SEPin input control
22 23 24
CDLR RST VDD1
Clock phase adjustment Reset input Power supply (+5 V)
No. 5966-3/24
LC74793, 74793JM
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pd max Topr Tstg VDD1 and VDD2 All input pins SDA, SYNCJDG, SEPOUT, DAV, HOUT, and VOUT Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD1 + 0.3 VSS - 0.3 to VDD1 + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Recommended Operating Conditions
Parameter Supply voltage Symbol VDD1 VIH1 High-level input voltage VIH2 VIH3 Low-level input voltage Pull-up resistance Composite video signal input voltage Input voltage VIL1 VIL2 RPU VIN1 VIN2 FOSC1 Oscillator frequency FOSC2 FOSC3 VDD1 and VDD2 SDA and SCL RST CTRL1 and CTRL2 RST, SDA, and SCL CTRL1 and CTRL2 RST SYNIN XtalIN (in external clock input mode) fin = fsc, 2fsc, or 4fsc VDD1 = 5 V VDD1 = 5 V Conditions Ratings min 4.5 0.8 VDD1 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 1.5 0.10 17.734 8.867 4.433 50 2.0 typ 5.0 max 5.5 5.5 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 2.25 5.0 Unit V V V V V V k Vp-p Vp-p MHz MHz MHz
The XtalIN and XtalOUT oscillator pins (4fsc: PAL) The XtalIN and XtalOUT oscillator pins (2fsc: PAL) The XtalIN and XtalOUT oscillator pins (fsc: PAL)
Note: Note that adequate measure must be taken to prevent noise from entering the XtalIN pin when it is used in clock input mode.
No. 5966-4/24
LC74793, 74793JM Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified.
Parameter Output off leakage current High-level output voltage Symbol Ileak2 VOH1 VOL1 Low-level output voltage VOL2 IIH Input current IIL Operating current drain IDD1 Applicable pins SDA and DAV SEPOUT, CPOUT, SYNCJDG, HOUT, and VOUT SEPOUT, CPOUT, SYNCJDG, DAV, HOUT, and VOUT SDA VDD1 = 4.5 V, IOH = -1.0 mA VDD1 = 4.5 V IOL = 1.0 mA VDD1 = 5.0 V IOL = 3.0 mA 3.5 1.0 0.4 1 -1 Conditions Ratings min typ max 1 Unit A V V V A A
RST, SDA, SCL, CTRL1, CTRL2, VIN = VDD1 VCOIN SDA, SCL, CTRL1, CTRL2, VCOIN VDD1 and VDD2 VIN = VSS1 With all outputs open and a 17.734 MHz crystal
40
mA
Timing Characteristics PDC and VPS Read and Write (I2C bus timing) at Ta = -30 to +70C, VDD1 = 50.5 V
Parameter SCL frequency Bus release time Start hold time SCL low-level period SCL high-level period Data hold time Data setup time Rise time Fall time Stop setup time Symbol fSCL tBUF tHD; STA tLOW tHIGN tHD; DAT tSU; DAT tR tF tSU; STO 4.0 4.7 4.0 4.7 4.0 0 250 1000 300 Conditions Ratings min typ max 100 Unit kHz s s s s s ns ns ns s
Supplementary Documentation * PDC and VPS serial timing (I2C bus timing)
S: Start condition P: Stop condition
No. 5966-5/24
I2C interface
Data latch circuit
Sync separator and data separator circuit Data acquisition circuit
LC74793, 74793JM
Vertical separator circuit AFC circuit (VCO) Timing generator
Synchronization recognition circuit
No. 5966-6/24
LC74793/M System Block Diagram
LC74793, 74793JM Control Commands The control commands have an 8-bit serial input format. Commands consist of a command identification code in the first byte and data in the following bytes. Command 0: Clock control command Command 1: VPS/PDC control command 1 Command 2: VPS/PDC control command 2 Command 3: Synchronizing signal detection command 1 Command 4: Synchronizing signal detection command 2 Command 5: Output control command 1 Command 6: Output control command 2 Command 7: VPS/PDC control command 3 Command 8: VPS/PDC control command 4 Command 9: VPS/PDC control command 5 Command 10: VPS/PDC control command 6 Display Control Commands: I 2C Write
First byte Command 7 COMMAND0 (Clock control) COMMAND1 (VPS/PDC control 1) COMMAND2 (VPS/PDC control 2) COMMAND3 (Synchronizing signal detection 1) COMMAND4 (Synchronizing signal detection 2) COMMAND5 (Output control 1) COMMAND6 (Output control 2) COMMAND7 (VPS/PDC control 3) COMMAND8 (VPS/PDC control 4) COMMAND9 (VPS/PDC control 5) COMMAND10 (VPS/PDC control 6) 1 1 1 1 1 1 1 1 1 1 1 Command ID code 6 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 Data 2 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 7 0 0 0 0 0 0 0 0 0 0 0 6 FS CPA 2 5 FS2 CPA 1 4 FS3 CPA 0 Second byte Data 3 O VPM 3 HBS 1 SN 3 SJN 2 SJ0 1 VI0 SET ECV 13 ECP 16 ECP 23 2 TST MOD VPM 2 BMS SN 2 SJN 1 SJ0 0 HI0 SET ECV 12 ECP 15 ECP 22 SLH 3 1 O VPM 1 EMS SN 1 SJC 1 VNP SEL V0T KST ECV 11 ECP 14 ECP 21 SLH 2 0 SYS RST VPM 0 DCE SN 0 SJC 0 VSP SEL H0T KST ECV 5 ECP 13 ECP 20 SLH 1
VMW VMW HBS SE2 SEL 2 RN 2 0 SP0 2 0 0 ECP 19 0 HXA LL2 RN 1 RNE 0 SP0 1 NP1 ECV 15 ECP 18 ECP 25 LKA SLC RN 0 SJN 3 SP0 0 NP0 ECV 14 ECP 17 ECP 24
MSK KMW H1
Once written, the first byte command identification code is retained until the next first byte is written. Data is written in second byte only continuous mode. (Automatic increment)
No. 5966-7/24
LC74793, 74793JM Command 0 (Clock Settings Command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 0 0 0 First byte identification bit Command 0 identification code. Clock settings. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- FS Contents Status 0 0 1 0 1 0 1 0 0 1 0 0 1 All registers are reset Normal operating mode Test mode This bit must be set to 0. FS 0 1 0 0 FS2 0 0 1 0 FS3 0 0 1 1 Setting 2FSC 4FSC (CDLR can be deleted) FSC 2FSC (CDLR can be deleted) Setting for the frequency input to the XtalIN pin (pin 2). CDLR can be deleted: The resistor connected to the CDLR pin may be removed. Second byte identification bit Function Notes
5
FS2
4 3 2 1 0
FS3 -- TSTMOD -- SYSRST
No. 5966-8/24
LC74793, 74793JM Command 1 (VPS/PDC control command 1) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 0 0 1 First byte identification bit Command 1 identification code. VPS/PDC control settings 1. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents Status 0 0 6 CPA1 1 0 5 CPA2 1 0 4 CPA0 1 Second byte identification bit CPA2 0 0 0 0 1 1 1 1 CPA1 0 0 1 1 0 0 1 1 CPA0 0 1 0 1 0 1 0 1 Clock NO1 NO2 NO3 NO4 NO5 NO6 NO7 NO8 Data acquisition clock selection. The clock can be shifted relative to the data in units of 8 clock cycles. Function Notes
0 3 VPM3 1
0 2 VPM2 1
0 1 VPM1 1
0 0 VPM0 1
M3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
MO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Operating mode VPS 8/30/2 (PDC) PDC and VPS automatic recognition 1 8/30/1 (UDT) Header time 1 Header time 2 Header time 3 Header time 4 Status display 1 Status display 2 Status display 3 Status display 4 PAL PULSE PDC and VPS automatic recognition 2 PDC and VPS automatic recognition 3 PDC and VPS automatic recognition 4
Slicer operating mode selection
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-9/24
LC74793, 74793JM Command 2 (VPS/PDC control command 2) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 0 1 0 First byte identification bit Command 2 identification code. VPS/PDC control settings 2. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- VMWSE2 Contents Status 0 0 1 0 1 0 1 0 1 0 2 BMS 1 1 EMS 0 1 Second byte identification bit From the vertical mask period start return period From 10H before the vertical mask period start return period The vertical mask period is the return period The vertical mask period is 9H Clock run discrimination 1 (2 times) Clock run discrimination 2 (4 times) Framing code discrimination 1 Framing code discrimination 2 (A single bad bit is ignored) Error check enabled (The error check can be turned on or off on per-byte basis.) Error check disabled (Applications can select whether data with errors is held or written for each byte.) Data hold Data write (Error bits are set to 0 in VPS mode) Error check turned on for unused bytes VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12 Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21. Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35. Error check turned off for unused bytes VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12 Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21. Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35. CPOUT pin vertical mask period switching 2 CPOUT pin vertical mask period switching Clock run discrimination circuit setting Function Notes
5
VMWSEL
4
HBS2
3
HBS1
Framing code discrimination selection When set to 0: If there are no errors in bytes for which the error check is turned on, those bytes will be written to P-S (COM7-9). When set to 1: Data is written to P-S regardless of whether or not errors occurred. When error checking is enabled, specifies the processing when an error occurs in a byte for which error checking was turned off
0 0 DCE 1
Error check setting for unused data bytes Biphase (VPS), Hamming (PDC), Odd parity (header)
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-10/24
LC74793, 74793JM Command 3 (Synchronizing signal detection command 1) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 0 1 1 First byte identification bit Command 3 identification code. Synchronizing signal detection settings 1. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- RN2 Contents Status 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SNO 0 1 0 0 0 Number of HSYNC detections No detection performed 32 64 128 256 External synchronizing signal detection control. Signal present absent discrimination. Sets the sampling period during which SYNC cannot be detected consecutively in the horizontal synchronizing signal period (1H). RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of HSYNC detections 0 (32) 4 (64) 8 (128) 16 (256) Second byte identification bit External synchronizing signal detection control. Signal absent present discrimination. Sets the sampling period during which SYNC is continuously detected in the horizontal synchronizing signal period (1H). Values in parentheses apply when RNE0 (COM4) is set to 1. Function Notes
5
RN1
4
RN0
3
SN3
2
SN2
1
SN1
0
SN0
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-11/24
LC74793, 74793JM Command 4 (Synchronizing signal detection command 2) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 1 0 0 First byte identification bit Command 4 identification code. Synchronizing signal detection settings 2. Function Notes
* Second byte
DA 0 to 7 7 6 5 Register -- -- RNE0 Contents Status 0 0 0 1 0 4 SJNS3 1 0 3 SJNS1 1 0 2 SJNS1 1 0 1 SJCS1 1 0 0 SJCS0 1 Note: All registers are cleared to 0 when the IC is reset by the RST pin. SJCS1 0 0 1 SJCS0 0 1 0 PAL 677 ns (1/3) 903 ns (1/4) 450 ns (1/2) NTSC 448 ns (1/2) 838 ns (1/3) 1117 ns (1/4) Synchronization discrimination. HSYNI signal switching clock selection. Synchronization signal discrimination absent preset: Normal values Synchronization signal discrimination absent preset: Values in parentheses SJNS3 0 0 0 0 1 1 1 1 SJNS2 0 0 1 1 0 0 1 1 SJNS1 0 1 0 1 0 1 0 1 Count None 4 8 16 32 64 128 256
Changes the values used for synchronizing signal discrimination in the absent preset direction (COM3).
Function Second byte identification bit
Notes
Setting for the noise exclusion circuit used for synchronizing signal discrimination in the absent preset direction. If the number of H signal inputs during a 1H period is greater than or equal to the value listed in the table, the IC determines that the signal is absent.
No. 5966-12/24
LC74793, 74793JM Command 5 (Output control command 1) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 1 0 1 First byte identification bit Command 5 identification code. Output control settings 1 Function Notes
* Second byte
DA 0 to 7 7 6 Register -- SPO2 1 0 5 SPO1 1 0 4 SPO0 1 0 3 SJO1 1 0 2 SJO0 1 1 VNPSEL 0 1 0 1 Vertical signal falling edge detection Vertical signal rising edge detection VSEP: About 8.9 s (NTSC) VSEP: About 17.8 s (NTSC) Vertical signal acquisition polarity switching. Only valid when internal vertical separation used. Internal vertical separation time switching Contents Status 0 0 Second byte identification bit SPO2 0 0 0 0 1 1 1 1 SPO1 0 0 1 1 0 0 1 1 SPO0 0 1 0 1 0 1 0 1 SEPout pin CSYNC Slice data amplitude O/E CLK (acquisition) VCO 1/1 VCO 1/2 VCO 1/3 VCO 1/4 Function Notes
SEPOUT (pin 18) output switching
SJO1 0 0 1 1
SJO0 0 1 0 1
SYNCJDG pin SYNCjdg LOCK SYNCdet DXout (Sliced data)
SYNCJDG (pin 8) output switching
0
VSPSEL
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-13/24
LC74793, 74793JM Command 6 (Output control command 2) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 1 1 0 First byte identification bit Command 6 identification code. Output control settings 2. Function Notes
* Second byte
DA 0 to 7 7 6 5 Register -- -- NP1 Contents Status 0 0 0 1 0 1 0 1 0 1 0 1 0 1 PAL NTSC 625 525 VSYNC signal output Set up as a general-purpose port HSYNC signal output Set up as a general-purpose port Negative polarity Positive polarity Negative polarity Positive polarity (Lo) (Hi) (Lo) (Hi) Number of scan lines Second byte identification bit Function Notes
4
NP0
3
VIOSET
VOUT mode setting
2
HIOSET
HOUT mode setting VOUT polarity selection. Level in parentheses applies when set up as a general-purpose port. HOUT polarity selection. Level in parentheses applies when set up as a general-purpose port.
1
VOTKST
0
HOTKST
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-14/24
LC74793, 74793JM Command 7 (VPS/PDC control command 3) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 0 1 1 1 First byte identification bit Command 7 identification code. VPS/PDC control settings 3. Function Notes
* Second byte
DA 0 to 7 7 6 5 Register -- -- ECV15 Contents Status 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Byte 15 biphase error check: on (data retained) Byte 15 biphase error check: off (data written) Byte 14 biphase error check: on (data retained) Byte 14 biphase error check: off (data written) Byte 13 biphase error check: on (data retained) Byte 13 biphase error check: off (data written) Byte 12 biphase error check: on (data retained) Byte 12 biphase error check: off (data written) Byte 11 biphase error check: on (data retained) Byte 11 biphase error check: off (data written) Byte 5 biphase error check: on (data retained) Byte 5 biphase error check: off (data written) VPS data specification when BMS is 0. Items in parentheses are the specification when BMS is 1. Second byte identification bit Function Notes
4
ECV14
3
ECV13
2
ECV12
1
ECV11
0
ECV5
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-15/24
LC74793, 74793JM Command 8 (VPS/PDC control command 4) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 1 0 0 0 First byte identification bit Command 8 identification code. VPS/PDC control settings 4. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents Status 0 0 6 ECP19 1 Second byte identification bit Byte 19 Hamming error check on (Data retained) {Bytes 44, 28, 36, 20, 32, 42, 32, 42} PDC data specification when BMS is 0. Items in parentheses are the specification when BMS is 1. Items in curly braces are the bytes for which the odd parity check is turned on or off for headers 1, 2, 3, and 4, and for status 1, 2, 3, and 4. Function Notes
Byte 19 Hamming error check off (Data written) {Bytes 44, 28, 36, 20, 32, 42, 32, 42}
0 5 ECP18 1
Byte 18 Hamming error check on (Data retained) {Bytes 43, 27, 35, 19, 31, 41, 31, 41}
Byte 18 Hamming error check off (Data written) {Bytes 43, 27, 35, 19, 31, 41, 31, 41}
0 4 ECP17 1
Byte 17 Hamming error check on (Data retained) {Bytes 42, 26, 34, 18, 30, 40, 30, 40}
Byte 17 Hamming error check off (Data written) {Bytes 42, 26, 34, 18, 30, 40, 30, 40}
0 3 ECP16 1
Byte 16 Hamming error check on (Data retained) {Bytes 41, 25, 33, 17, 29, 39, 29, 39}
Byte 16 Hamming error check off (Data written) {Bytes 41, 25, 33, 17, 29, 39, 29, 39}
0 2 ECP15 1
Byte 15 Hamming error check on (Data retained) {Bytes 40, 24, 32, 16, 28, 38, 28, 38}
Byte 15 Hamming error check off (Data written) {Bytes 40, 24, 32, 16, 28, 38, 28, 38}
0 1 ECP14 1
Byte 14 Hamming error check on (Data retained) {Bytes 39, 23, 31, 15, 27, 37, 27, 37}
Byte 14 Hamming error check off (Data written) {Bytes 39, 23, 31, 15, 27, 37, 27, 37}
0 0 ECP13 1
Byte 13 Hamming error check on (Data retained) {Bytes 38, 22, 30, 14, 26, 36, 26, 36}
Byte 13 Hamming error check off (Data written) {Bytes 38, 22, 30, 14, 26, 36, 26, 36}
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-16/24
LC74793, 74793JM Command 9 (VPS/PDC control command 5) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 1 0 0 1 First byte identification bit Command 9 identification code. VPS/PDC control settings 5. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- -- Contents Status 0 0 0 5 ECP25 1 0 1 0 1 0 2 ECP22 1 Byte 25 Hamming error check off (Data written) Byte 24 Hamming error check on (Data retained) Byte 24 Hamming error check off (Data written) Byte 23 Hamming error check on (Data retained) Byte 23 Hamming error check off (Data written) Byte 22 Hamming error check on (Data retained) {Bytes , , , , 35, 45, 35, 45} Byte 25 Hamming error check on (Data retained) PDC data specification when BMS is 0. Items in parentheses are the specification when BMS is 1. Items in curly braces are the bytes for which the odd parity check is turned on or off for headers 1, 2, 3, and 4, and for status 1, 2, 3, and 4. Second byte identification bit Function Notes
4
ECP24
3
ECP23
Byte 22 Hamming error check off (Data written) {Bytes , , , , 35, 45, 35, 45}
0 1 ECP21 1
Byte 21 Hamming error check on (Data retained) {Bytes , , , , 34, 44, 34, 44}
Byte 21 Hamming error check off (Data written) {Bytes , , , , 34, 44, 34, 44}
0 0 ECP20 1
Byte 20 Hamming error check on (Data retained) {Bytes 45, 29, 37, 21, 33, 43, 33, 43}
Byte 20 Hamming error check off (Data written) {Bytes 45, 29, 37, 21, 33, 43, 33, 43}
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-17/24
LC74793, 74793JM Command 10 (VPS/PDC control command 6) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents Status 1 1 1 1 1 0 1 0 First byte identification bit Command A identification code. VPS/PDC control settings 6. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- HXALL2 Contents Status 0 0 1 0 1 0 1 0 1 0 2 SLH3 1 0 1 SLH2 1 0 0 SLH1 1 Forcibly set to high or low only during the CSYNC period MODE 0 1 2 3 4 5 6 7 S321 00 01 10 11 00 01 10 11 Clock discrimination 11xx0000 00xx1111 1xxx0000 0xxx1111 11110000 00001111 000x 111x AFC: A mask is applied to the horizontal signal Second byte identification bit Slice data discrimination time: Normal Discriminates the vertical return period data in all modes Normal operation Always in the locked state VPS/PDC data discrimination period setting Function Notes
5
LKASLC
4 3
MSKH1 KMW
0 0 0 0 1 1 1 1
1 0 1 0 x x 1 0
1 0 1 0 x x 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 x x
0 1 0 1 0 1
0 1 x x 0 1
x x x x x x
x x x x x x
Clock discrimination method switching
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5966-18/24
LC74793, 74793JM PDC/VPS Output Data Format Data is read out in order starting with bit 7 of byte 1.
Output data Byte1 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 byte15 PDC 8/30/mode Format1 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 byte16 Format2 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 bit0 1 2 3 byte11 VPS mode bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 Header time mode 1 (3) byte38 (30) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 Header time mode 2 (4) byte22 (14) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7
byte17
Byte2
byte16
byte18
byte12
byte39 (31)
byte23 (15)
byte19
Byte3
byte17
byte20
byte13
byte40 (32)
byte24 (16)
byte21
Byte4
byte18
byte22
byte14
byte41 (33)
byte25 (17)
byte23
Byte5
byte19
byte14
byte5
byte42 (34)
byte26 (18)
byte15
Byte6
byte20
byte24
byte15
byte43 (35)
byte27 (19)
byte25
Continued on next page.
No. 5966-19/24
LC74793, 74793JM
Continued from preceding page.
Output data Byte7 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 byte21 PDC 8/30/mode Format1 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 byte13 Format2 bit0 1 2 3 1 1 1 1 1 1 1 0 Error information byte11 12 13 14 5 15 VPS mode Header time mode 1 (3) byte44 (36) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 Header time mode 2 (4) byte28 (20) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7
1 1 1 1 Error information 1 byte16 17 18 19 20 21 22 23 byte14 15 24 25 13
Byte8
byte13
byte45 (37)
byte29 (21)
0 0
Byte9
byte14
Error information 2
0 0 0
Error byte38 (30) information 39 (31) 40 (32) 41 (33) 42 (34) 43 (35) 44 (36) 45 (37)
Error byte22 (14) information 23 (15) 24 (16) 25 (17) 26 (18) 27 (19) 28 (20) 29 (21)
Byte10
byte22
Byte11
byte23
Byte12
byte24
Byte13
byte25
Note: Data with the value 1 is output for sections for which there is no output data setting.
No. 5966-20/24
LC74793, 74793JM Data is read out in order starting with bit 7 of byte 1. Status display 1 and 2: 8/30/2 Status display 1 and 2: 8/30/1
Output data Byte1 Bit7 6 5 4 3 2 1 0 Byte2 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 byte27 (27) Status display mode 1 (3) Status display mode 2 (4) byte26 (26) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 byte37 (37) byte36 (36) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 PAL Puls bit0 1 2 3 4 5 6 7 bit8 9 10 11 12 13 0 0
Byte3
byte28 (28)
byte38 (38)
Byte4
byte29 (29)
byte39 (39)
Byte5
byte30 (30)
byte40 (40)
Byte6
byte31 (31)
byte41 (41)
Note: Data with the value 1 is output for sections for which there is no output data setting.
Continued on next page.
No. 5966-21/24
LC74793, 74793JM
Continued from preceding page.
Output data Byte7 Bit7 6 5 4 3 2 1 0 Byte8 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 Bit7 6 5 4 3 2 1 0 byte33 (33) Status display mode 1 (3) Status display mode 2 (4) byte32 (32) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 byte43 (43) byte42 (42) bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 bit0 1 2 3 4 5 6 7 PAL Puls
Byte9
byte34 (34)
byte44 (44)
Byte10
byte35 (35)
byte45 (45)
Byte11
Error byte26 (26) information 1 27 (27) 28 (28) 29 (29) 30 (30) 31 (31) 32 (32) 33 (33) Error byte34 (34) information 2 35 (35) 0 0 0 0 0 0
Error byte36 (36) information 1 37 (37) 38 (38) 39 (39) 40 (40) 41 (41) 42 (42) 43 (43) Error byte44 (44) information 1 45 (45) 0 0 0 0 0 0
Byte12
Byte13
Note: Data with the value 1 is output for sections for which there is no output data setting.
No. 5966-22/24
LC74793, 74793JM Sample Application Circuit * Using an external system clock
Microcontroller
No. 5966-23/24
LC74793, 74793JM * Using a crystal oscillator
Microcontroller
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 5966-24/24

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